Conventionally, semiconductor packages have been manufactured from assembling semiconductor dice on substrates in the form of lead frames. Such substrates support the semiconductor dice during die bonding, wire bonding and encapsulation of the dice and wire bonds. After encapsulation, the substrates and encapsulant are cut or singulated to form separate semiconductor packages.
Driven by portable devices, wearable devices and other consumer products, there is an increasing demand in the semiconductor packaging industry to produce devices with smaller form factors. To do so, thinner substrates which are more compact and have routable circuits are required to attain the objects of such cost-effective advanced packaging solutions.
For instance, U.S. Pat. No. 7,795,071 entitled “Semiconductor Package for Fine Pitch Miniaturization and Manufacturing Method thereof” discloses a fine pitch semiconductor manufacturing package substrate and a process using the substrate. Conductive electrical traces are embedded in and isolated by an insulating layer on a carrier, after which the carrier is selectively etched to create a finished product.
A problem with the said approach is that, for very thin package substrates, such as those which are 100 μm or thinner, many challenges such as warpage or cracks in the substrate are encountered during the manufacturing of the substrate, as well as during its handling in the semiconductor assembly process. These lead to lower yield and higher costs, and impose limitations on the ability to make the semiconductor packages even thinner.